Traditional stencil-based technologies for fine electrolytic pitch bumping (e.g., Micro-ball bumping or Solder Paste Printing) are reaching scaling limits as pitches become finer in semiconductor packaging. For high bandwidth connectivity packaging, bumping is needed for varying pitch and solder resist opening (SRO) layer sizes, and the traditional stencil methods do not work for these types of technologies. Further, electrolytic plating can be used to overcome some of the deficiencies of stencil-based technologies, but is much more costly (e.g., use of gold and many complex process steps) and has several limitations, including dry film resist (DFR) compatibility with bump plating bath, stripping of the DFR and seed layer without damaging the bump and the DFR adhesion to the seed layer at finer pitches. Traditional technologies may use gold during the process of forming a conductive bump. Thus, improved methods and devices are desirable to address issues including, but not limited to, reduction in manufacture costs and variable solder bump pitch.